`include "common.svh"
module dispatch_test #(
    parameter DISPATCH_WIDTH = 3
) (
    input clk,
    input rst,

    input i_valid,
    input FU_Type i_rop_fu_type[DISPATCH_WIDTH-1:0],
    input word_t i_rop_pc[DISPATCH_WIDTH-1:0],
    input i_rop_valid[DISPATCH_WIDTH-1:0],
    output i_ready,
    // TO ROB
    output o_rob_write_valid,
    output o_rob_write_op_valid[DISPATCH_WIDTH-1:0],
    output ROB_Entry o_rob_write_op[DISPATCH_WIDTH-1:0],
    output word_t o_rob_write_op_pc[DISPATCH_WIDTH-1:0],
    input ROB_PTR o_rob_write_rob_idx[DISPATCH_WIDTH-1:0],
    input o_rob_write_ready,
    //TO ALU
    output o_alu_valid[DISPATCH_WIDTH-1:0],
    output RenamedOP o_alu_rop[DISPATCH_WIDTH-1:0],
    output word_t o_alu_rop_pc[DISPATCH_WIDTH-1:0],
    output ROB_PTR o_alu_rop_rob_idx[DISPATCH_WIDTH-1:0],
    input o_alu_ready,
    //TO BRU
    output o_bru_valid[DISPATCH_WIDTH-1:0],
    output RenamedOP o_bru_rop[DISPATCH_WIDTH-1:0],
    output word_t o_bru_rop_pc[DISPATCH_WIDTH-1:0],
    output ROB_PTR o_bru_rop_rob_idx[DISPATCH_WIDTH-1:0],
    input o_bru_ready,
    //TO LSU
    output o_lsu_valid[DISPATCH_WIDTH-1:0],
    output RenamedOP o_lsu_rop[DISPATCH_WIDTH-1:0],
    output word_t o_lsu_rop_pc[DISPATCH_WIDTH-1:0],
    output ROB_PTR o_lsu_rop_rob_idx[DISPATCH_WIDTH-1:0],
    input o_lsu_ready,
    //TO MDU
    output o_mdu_valid[DISPATCH_WIDTH-1:0],
    output RenamedOP o_mdu_rop[DISPATCH_WIDTH-1:0],
    output word_t o_mdu_rop_pc[DISPATCH_WIDTH-1:0],
    output ROB_PTR o_mdu_rop_rob_idx[DISPATCH_WIDTH-1:0],
    input o_mdu_ready,
    //TO MISC
    output o_misc_valid[DISPATCH_WIDTH-1:0],
    output RenamedOP o_misc_rop[DISPATCH_WIDTH-1:0],
    output word_t o_misc_rop_pc[DISPATCH_WIDTH-1:0],
    output ROB_PTR o_misc_rop_rob_idx[DISPATCH_WIDTH-1:0],
    input o_misc_ready

);
  RenamedOP i_rop[DISPATCH_WIDTH-1:0];
  always_comb begin
    integer i;
    for (i = 0; i < DISPATCH_WIDTH; i = i + 1) begin
      i_rop[i] = 'b0;
      i_rop[i].fop.dop.fu_type = i_rop_fu_type[i];
      i_rop[i].fop.pc = i_rop_pc[i];
    end

  end
  genvar gi;
  generate

    for (gi = 0; gi < DISPATCH_WIDTH; gi = gi + 1) begin
      assign o_rob_write_op_pc[gi] = o_rob_write_op[gi].rop.fop.pc;
      assign o_alu_rop_pc[gi] = o_alu_rop[gi].fop.pc;
      assign o_bru_rop_pc[gi] = o_bru_rop[gi].fop.pc;
      assign o_lsu_rop_pc[gi] = o_lsu_rop[gi].fop.pc;
      assign o_mdu_rop_pc[gi] = o_mdu_rop[gi].fop.pc;
      assign o_misc_rop_pc[gi] = o_misc_rop[gi].fop.pc;
    end
  endgenerate
  dispatch #(DISPATCH_WIDTH) inst_dispatch (.*);
endmodule
